Integrated circuits are an integral part of any electronic device. A variety of integrated circuits are often used together to enable the operation of the electronic device. While integrated circuits are typically designed for a particular application, one type of integrated circuit which enables flexibility is a programmable logic device (PLD). A programmable logic device is designed to be user-programmable so that users may implement logic designs of their choices. One type of programmable logic device is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” having a two-level AND/OR structure connected together and to input/output (I/O) resources by an interconnect switch matrix. Another type of programmable logic device is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLDs also have different “modes” depending on the operations being performed on them. A specific protocol allows a programmable logic device to enter into the appropriate mode. Typical PLDs have internal blocks of configuration memory which specify how each of the programmable cells will emulate the user's logic. During a “program” mode, a configuration bitstream is provided to non-volatile memory, such as a read-only memory (ROM) (e.g. a programmable ROM (PROM), an erasable PROM (EPROM), or an electrically erasable PROM (EEPROM)) either external or internal to the programmable logic device. Each address is typically accessed by specifying its row and column addresses. During system power up of a “startup” mode, the configuration bits are successively loaded from the non-volatile memory into static random access memory (SRAM) configuration latches of a configurable logic block.
As will be described in more detail in references to specific embodiments of the invention, various blocks of a PLD are repeated in the device. One example of such a block is a block implementing a multiplier/accumulator (MACC), which is used in digital signal processor (DSP) blocks. In order to provide a PLD having DSP functionality to a customer, it is important that the DSP blocks are tested to determine that they are functioning properly. One aspect of testing a DSP block is to determine whether the inputs to a DSP block are correctly receiving input signals. That is, it is necessary to determine whether the paths from a source of the input signals to the inputs of the circuit are enabling the input signals to arrive at the inputs of the circuit. While the test itself is important in any device implementing DSP blocks, the test is particularly beneficial in a programmable logic device, where programmable interconnects enable paths to the inputs to be re-routed if the correct input signals are not arriving at the inputs.
Conventional methods of testing the paths to the inputs of a DSP block or other circuit block require placing a multiplexer at the output, where the multiplexer is coupled to receive the block inputs and the block output. In particular, as shown in FIG. 1, a conventional circuit may include multiplexers outside of the DSP block to select either a bit of the output of the DSP, or an input bit. During test, configuration bits functioning as select lines for the multiplexers are used to connect the block inputs to the output through the multiplexer. For example, four multiple-bit inputs A-D which are couple to the DSP block are also routed to a group of multiplexers, each receiving one bit of each of the inputs A-D. The disadvantage of circuit of FIG. 1 is that the insertion of the multiplexers reduces performance by adding extra gates. The circuit of FIG. 1 also adds more load to the DSP block, and delays the inputs into the DSP block from programmable interconnects and from the output of the DSP block to the programmable interconnects. The additional multiplexers may also lead to a substantial increase in size of the circuit required to implement a DSP.
Accordingly, there is a need for a way to verify all of the inputs coupled to a circuit block, while minimizing the circuit requirements and the impact of the circuits testing the inputs on the performance of the circuit block.